The frontend interface is provided as an FPGA core library. A rough definition of the data passing between detector side logic and Belle2link transmitter is shown as below:
-- RyosukeItoh - 22 Nov 2010 | I | Attachment | Action | Size | Date | Who | Comment |
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belle2link.png | manage | 350.0 K | 22 Nov 2010 - 07:36 | RyosukeItoh | |
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receivers.png | manage | 2282.6 K | 22 Nov 2010 - 08:00 | RyosukeItoh | |
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transmitter.png | manage | 2463.0 K | 22 Nov 2010 - 08:23 | RyosukeItoh |